In designing complex circuitry such as application-specific integrated circuits ("ASICs"), the designed logic of such circuitry is typically simulated in a computer using data and computer programs to thereby test the viability and accurate performance of the designed logic. By doing so, design flaws can be detected prior to expending the time and engineering and financial resources required to physically build the circuitry. To simulate circuitry using data and computer programs, the circuitry is described in a hardware description language ("HDL") to form a model. One example of an HDL is the Verilog HDL processed by the Cadence Verilog hardware simulator available from Cadence Design Systems, Inc. of San Jose, Calif. The HDL model of a circuit typically includes a description of components of the state of the circuit and a description of the behavior of the circuit. The behavior of the circuit generally includes inter-relationships between various components of the state of the circuit.
A hardware simulator then uses the HDL model of the circuitry to simulate the circuitry. The hardware simulator is a computer process which accepts data defining signals to be placed on certain parts of the simulated circuit and then changes the state of the circuit in accordance with the signals. The certain parts of the circuit include, for example, terminals, lines, or registers of the simulated circuit.
Circuitry which is simulated in this manner is becoming increasingly complex reducing significantly the feasibility of simulation of such circuitry on a single computer processor. Factors which contribute significantly to such reduction in feasibility in simulations of particularly complex circuits include intolerable amounts of time and computer resources which are required for such complex simulations to execute. For example, simulating a particularly complex circuit in a single computer may require more memory than is available within the single computer. The Virtual Bus Application describes a mechanism by which a complex circuit is divided into multiple circuit parts according to portions of the complex circuit which interact with one another through a bus and the circuit parts are simulated by individual models which can execute of multiple constituent computers of a computer network. According to the mechanism described in the Virtual Bus Application, the bus is simulated collectively by a number of virtual bus stubs, each of which is associated with and interacts with a respective model of a circuit part, and a resolver. The resolver collects simulated bus signals from each of the virtual bus stubs, resolves from the collected simulated bus signals a single, resolved simulated state of the bus, and transmits to each of the virtual bus stubs simulated bus signals corresponding to the resolved simulated bus state.
In simulating particularly complex circuits, the mechanism described in the Virtual Bus Application is susceptible to deadlock situations. The following example is illustrative. Circuit 100 (FIG. 1) includes circuit parts 102A-C. Circuit parts 102A-C are coupled to, and communicate with one another through, a bus 106. In addition, circuit parts 102A and 102B are coupled to, and communicate with one another through, a bus 104. A distributed simulation 200 of circuit 100 is shown in FIG. 2. Bus 106 (FIG. 1) is represented by virtual bus stubs ("VBSs") 206A-C (FIG. 2) of simulation systems 208A-C, respectively. Simulation systems 208A-C include circuit models 202A-C, respectively, which represent circuit parts 102A-C (FIG. 1), respectively. Bus 104 (FIG. 1) is represented by VBSs 204A (FIG. 2) and 204B of simulation systems 208A and 208B, respectively.
A deadlock situation can occur as follows. Assume that VBS 206A and VBS 204B post simulated bus signals corresponding to busses 106 and 104, respectively, at precisely the same simulation time. As a result of posting by VBS 206A, execution of simulation system 208A is suspended pending posting by VBSs 206B and 206C of simulated bus signals corresponding to bus 106. However, VBS 206B cannot post such simulated bus signals because execution of simulation system 208B is suspended pending posting by VBS 204A of simulated bus signals corresponding to bus 104 as a result of posting by VBS 204B. As described above, execution of simulation system 208A is suspended, so VBS 204A cannot post such simulated bus signals. Simulation 200 is therefore deadlocked. Deadlock is a catastrophic error and must be either resolved so that execution of simulation 200 can proceed or avoided altogether.
A number of deadlock resolution mechanisms are known; however, such mechanisms are generally quite complex and expensive, in terms of time, effort, and computer resources, to implement. A number of deadlock avoidance mechanisms are also known; however, characteristics of hardware simulation make implementation of conventional deadlock avoidance mechanisms particularly difficult. Specifically, engineers which implement simulations such as distributed simulation 200 often program stop points in simulation systems such as any of simulation systems 208A-C such that the simulated state of any one of circuit parts 102A-C can be examined and analyzed. In general, including stop points in a simulation can cause deadlock of the simulation. Suppose, for example, that simulation systems 208A-C are programmed to stop execution at a particular simulation time, e.g., 500 simulated microseconds from the beginning of the simulation. If VBS 204A posts while simulation system 208B is stopped at a stop point the simulation is deadlocked since simulation system 208A cannot resume execution until VBS 204B of simulation system 208B posts and VBS 204B cannot post since execution of simulation system 208B is stopped at the stop point.
What persists in the art as an unsatisfied need is a deadlock avoidance mechanism which prevents deadlock situation in distributed bus stubs which collected simulate a bus (i) through which two or more circuit parts communicate, (ii) which is relatively simple to implement, and (iii) which is simultaneously effective and does not interfere with a test developers ability to insert stop points in any hardware simulation to thereby examine and/or analyze the simulation of a circuit part.